This invention relates to a flat-panel display unit which is connected to equipment such as a personal computer which generates image information through digital processing, and more particularly to a flat-panel display unit which samples an image data signal from equipment such as a personal computer and stores the sampled data in an image memory.
It is a recent trend that a display unit having a flat display screen, e.g., a liquid crystal panel or an EL (electroluminescent) panel, is used in connection with a personal computer or the like. In such flat-panel display units, it is necessary to decrease the cycle of driving the display screen to obtain sufficient contrast. However, the scanning period of display signals sent from a personal computer is not always coincident with the scanning period of the display unit. To decrease the duty cycle, the display unit can be divided into two areas, i.e., upper and lower areas, which are driven separately. Accordingly, when the display unit receives image data for one picture to be displayed, which data is outputted from the personal computer, the image data are divided into two parts, i.e., upper area data and lower area data to be scanned respectively in the upper and lower areas. As a result, the scanning period of the signal from the personal computer is not coincident with the scanning period of the display unit.
Thus, it is necessary to carry out conversion of the scanning period by some appropriate means, and conversion of the scanning period is usually carried out using an image memory. To be more specific, in the display unit, an image data signal is sampled, then stored in the image memory, and read out with the read-out timing being adjusted to the scanning timing of the display unit.
Each different model of personal computer or the like generally has its own unique dot clock pulse rate, image data being sent to the associated display unit synchronized with the dot clock pulse. Accordingly, in order to sample the image data in the display unit, it is required to sample the image data with a sampling clock pulse synchronized with the dot clock pulse from the personal computer or the like. If synchronization is not achieved, the quality of the displayed image becomes low due to drop-out or doubling of the data to be displayed.
In addition, a sampling clock pulse generator for generating a sampling clock pulse for sampling the data signal is provided. It is conventional to use a generator such as that shown in FIG. 1, which is disclosed in a publication entitled "Digital Technology in Broadcasting" (published by Japan Broadcasting Publishing Co., Ltd.. on Dec. 20, 1982, pages 164-165).
In FIG. 1, reference numeral 31 denotes a phase comparator; 32 denotes a voltage-controlled oscillator (VCO); 33 denotes a divider; 11 denotes a synchronizing signal and 14 denotes a sampling clock pulse for sampling an image data signal. Given that the period of the horizontal synchronizing signal is 800 times the period of the dot clock pulse, the sampling clock pulse 14, which is an output of the VCO 32, is divided in frequency by a factor of 1/800 by the divider 33, then is inputted to the phase comparator 31, and a phase difference between it and the horizontal synchronizing signal is detected. The VCO 32 is controlled so as to reduce the phase difference by the output of the phase comparator 31 and, as a result, a sampling clock pulse 14, synchronized with the horizontal synchronizing signal 11 is generated. This method is the so-called PLL (phase-locked-loop) method.
The PLL method is widely used to obtain a signal synchronous with an external signal, but the signal produced using this method is very sensitive to variations in external factors such as ambient temperature, ambient noise, etc. Accordingly, a problem exists in that disturbances of the oscillating frequency, phase jitter and the like can occur easily due to unlocking of the loop, which results in drop-out or doubling of the data on the display screen of the display unit.
FIG. 2 is a view explaining how the above problem occurs. Under the normal operation of the sampling clock pulse generator, the N-th image data 15 are supposed to be sampled by the rising edge of the N-th sampling clock pulse 14 as shown in the drawing, and the N+1-th image data 15 are sampled by rising edge of the N+1-th pulse 14. However, in the event that the N-th pulse is dislocated or shifted to a position shown by the broken line due to variations in external factors as described above, the N+1-th data 15 are sampled instead of the N-th image data, and consequently the N-th image data 15 are not sampled at all. As a result, problems such as drop-out are manifested on the display screen of the display unit.